1. Field of the Invention
The present invention is in the field of integrated circuits, particularly directed to on-chip timing, and is more specifically directed to programming sense amplifier timing and edge transition detection pulse width during production testing of semiconductor memory arrays.
2. Description of the Prior Art
A primary concern in the construction of semiconductor memories is how to achieve optimum device performance while maximizing yields and minimizing manufacturing costs. Many types of semiconductor memories are containing greater numbers of storage locations, higher capacity, and faster operating speeds as the manufacturing technology improves. For example, static random access memories (SRAMs) having 2.sup.20 storage locations (i.e., 1 Mbits) and dynamic random access memories (DRAMs) having 2.sup.22 storage locations (i.e., 4 Mbits) are available in the market, running at operational speeds in excess of 100 MHz. Additional high-density memories include FIFOs, dual-port memories, and read-only memories of various types, fabricated as individual components and embedded in other integrated circuits such as microprocessors and other logic devices.
These high-density memories, however, are usable only if each and every data storage location or "bit" can be timely accessed and store both digital data states. Failure of a single bit may cause the entire memory device (and logic device having an embedded memory) to be non-marketable, thereby increasing manufacturing costs and decreasing yields.
Although strict controls are exercised during device fabrication, process conditions and the surrounding environment cannot be reproduced without variation. Therefore, the resulting memory devices inevitably have a diversity of performance levels such as differing set-up times, hold times, and operational speeds. As the industry continues to push for larger capacity, faster semiconductor devices, the need for cost efficient testing and repair methods increases to overcome the yield decrease attributable to manufacturing variations.
Present testing and repair methods do not facilitate cost efficient high speed testing of a device and subsequent retesting at a slower operational speed. If a part fails merely because a timed command signal received an address, sent a pulse or latched data before an adequate signal was presented, the part must be scrapped even though it could have passed a subsequent test utilizing a delayed mode. Conventional methods of introducing delays to critical signals include using experimental masks, focused ion beam (FIB) adjustment, or placement of fuses in each delay circuit. These methods, however, are nonadjustable, costly, time consuming and prone to error. Therefore, a trade-off must be made between faster parts or higher manufacturing yields.
Consider, for example, an SRAM device incorporating a dynamic, clocked "DRAM-style" sense amplifier such as a fast cache SRAM memory device. This style of sense amplifier has multiple advantages over other styles including faster speeds and lower power consumption. However, it cannot "recover" its output if it sensed erroneous data. To "recover" a sense amplifier means to change its output during the same clocking cycle if the initial data sensed was incorrect. Therefore, if the sense amplifier prematurely reads data on an otherwise properly functioning device, the die fails and the part must be discarded.
At the wafer fabrication level, production testing exercises the device's operation including sense amplifier enablement. In an effort to increase production yields and prevent failures attributable to premature sensing, present design guard banding practices include conservatively "clocking" the sense amplifier for a worst case time delay. Such clocking takes into consideration process variations, temperature and voltage ranges, to render maximum device functionality over a broad distribution range. Although delayed clocking of the sense amplifier ensures that an adequate signal has built up on the bit lines before the data is read, such a method has the disadvantage of globally slowing down the operational speed of the potentially faster RAMs in the distribution of devices.
Next, consider the situation which arises during the design and manufacture of a new product still under development. Defects may be present particularly during the early development stages of a fabrication process which randomly render isolated bits slower than the remainder of the bits on the part. For example, a new process may successfully allow fabrication of a faster device where approximately ninety-nine percent of the bits function at the faster operational speed and only one percent operate at a slightly slower rate. Since the industry does not have the means for efficiently retesting slower parts, the entire die must be scrapped if an internal pulse was too short or an on-chip signal operated too quickly.
Thus, present testing methods require a trade off between faster operational speeds and higher manufacturing yields. Aggressive timing allows faster parts but lower yields. Conservative timing improves yields but slows down the fastest possible parts.
Therefore, it would be desirable to have a method and circuit for nonpermanently testing, manipulating, and programming the delay or width of a timed command signal enabling the identification of faster parts while maintaining high manufacturing yields in a production environment.